1. Field of the Invention
The invention relates to the process of fabricating integrated circuits. More specifically, the invention relates to a method and an apparatus for providing feedback from a compactor to a router to facilitate layout of an integrated circuit.
2. Related Art
Recent advances in integrated circuit technology have largely been accomplished by decreasing the feature size of circuit elements on a semiconductor chip. As the feature size of these circuit elements continues to decrease, circuit designers are forced to deal with problems that arise in placing ever larger numbers of circuit elements on a semiconductor die.
The process of fabricating an integrated circuit starts with a circuit design. The elements of this circuit design are first placed to form an initial layout of the integrated circuit. Next, a router adds traces to the layout to connect these elements together. After the router has finished, the layout is compacted to produce a final layout.
Note that in some systems, the router relaxes strict design rule check (DRC) correctness to enable a routing to be generated successfully. In these systems, the compactor is subsequently responsible for enforcing strict DRC correctness. This approach typically works well. However, in many cases a routing is generated successfully but contains infeasibilities, which cannot be resolved by the compactor.
When the compactor encounters an infeasibility, a new placement is typically routed and compacted in an attempt to overcome the infeasibilities. This process is repeated as many times as is necessary to produce an acceptable layout. Because of the large number of circuit elements that can be incorporated into a modern integrated circuit, this process can be extremely time consuming.
Hence, what is needed is a method and an apparatus for generating a layout for an integrated circuit without the problems described above.